1. Field of the Invention
This invention relates generally to designing systems for digital signal processing and the like. More specifically, the present invention relates to compensating for clock drift and jitter in Farrow based sampling rate conversion. The present invention can be used in connection with programmable or otherwise configurable devices, including programmable logic devices.
2. Description of Related Art
In many instances, electronic design automation (EDA) includes use of components, blocks, etc. that employ distinct clocks and sampling rates. The well known Farrow structure provides a means of implementing digital sampling rate conversion on a parameterizable hardware platform, enabling adaptation of a converter to different rate change factors. Prior sampling rate converters using the Farrow structure can only convert the sampling rate when there is a fixed relationship between input sampling rate and output sampling rate, as is the case when both clocks are derived from the same phase-locked loop (PLL). When one clock drifts slightly from its nominal frequency, the Farrow structure will start to skip samples, introducing distortion in the sampled data stream.
For example, a first (for example, input) nominal sampling rate is 30 kHz. This first clock's actual sampling rate also is 30 kHz. The second (for example, output) clock's nominal sampling rate is 20 kHz; but the second clock's actual sampling rate is 18 kHz. A Farrow structure converter will write data to an output (for example, a FIFO buffer) using a nominal phase offset of ⅔, based on the first and second nominal sampling rates. However, because the second clock's actual sampling rate is 18 kHz, excess data will accumulate at the converter's output, eventually causing valid data to be overwritten when the buffer overflows. In a case where the second actual sampling rate is 22 kHz, a different problem arises. In that case, the second clock will read data out from the output faster than the data is being written, leading to buffer “leaking” and a depletion of data in the FIFO until it is empty. Both of these types of scenarios lead to serious problems for the device(s) using the converted data downstream.
FIG. 1 is a schematic showing a prior Farrow structure used in connection with a polyphase filter. The view of FIG. 1 is divided into two clock (sampling rate) domains. A first domain 102 operates at a first clock rate, while the second domain 104 operates at a second clock rate. These boundaries do not actually exist, but are provided as conceptual guides for purposes of this disclosure. Data using the first clock rate is converted by a Farrow structure, written to the Farrow structure output and subsequently read out into the second clock domain 104.
In the illustrative system of FIG. 1, a polyphase filter 110 provides 3 separately filtered versions of the input signal 112. Farrow structure combiner 120 receives signals 114 as its input, combines the 3 phases and generates the desired result at its output 122. Data converted to the second clock sampling rate at Farrow structure output 122 is delivered to a sampling rate transition interface 130 (which could be a device, such as a FIFO buffer, which would use a “wr” control value for writing valid converted data to the buffer and a “rd” value for reading valid converted data from the buffer), where the data becomes accessible to the second sampling rate domain 104.
To assist the Farrow combiner 120 in converting sampling rates, a phase offset (μ) generator 140 uses a phase offset μ to correct for phase differences due to the different clock/sampling rates and to control writing of valid data to the transition interface 130 (for example, by using a “wr” value in connection with a FIFO buffer). Strictly speaking, μ is the phase difference between the input phase and the desired output phase of Farrow structure 120. It typically is the difference between the two sampling rates (counter values), scaled to the range of 0 to 1 (where 1 represents a full phase cycle). In the example of FIG. 1, the phase offset is determined and supplied by a phase offset calculator 150.
In a sampling rate conversion of 10/9 (that is, where 9 samples will be read as output for every 10 samples written as input to a FIFO, for example), μ may have a value that varies from 1 down to 0. When μ is 1, the output is delayed by exactly one sample. As μ decreases toward 0, the output moves closer to the values that would be presented if no μ offset was used at all, a delay of 0 samples.
Eventually, after 10 clock cycles in this example, there is an overflow and μ resets to 1. When this happens the same sample is obtained twice. Every time this happens, the superfluous sample is marked for deletion. Thus, using μ based on the 10/9 conversion rate, for each 10 samples at the input, 9 valid samples plus one invalid sample are generated at the output. When the valid output samples are written as inputs to transition point 130, 9 samples are written and the single invalid sample is skipped. On the output side of point 130, the data can now be read at 9/10 of the input sampling rate, receiving a signal of the same frequency, sampled at 9/10 of the input sampling rate.
The problem with these earlier systems is that the clock ratios and/or sampling rates are assumed to be and/or are defined as constants (their respective nominal sampling rates)—that is, sampling/clock rates that match their nominal rates and do not vary relative to one another. No accommodation and/or compensation is or can be made for a drift over time of the input and/or output clock and/or any variance from the clocks' stated nominal rates. As noted above, when such drifts and/or variances do occur (and they do), the FIFO overruns or underruns, depending on which clock is faster. Thus, where the actual rates differ from the nominal rates even marginally, as typically is the case when two clocks are not based on the same PLL, FIFO overruns or underruns occur, which significantly degrades the quality of the produced sample stream.
Current systems are intended to work with sample clocks that are derived from the same PLL. Using just one PLL means that the two clocks cannot drift in respect to each other. A small amount of phase jitter is allowed, and is easily compensated for in the FIFO. Data samples are written into the FIFO until the FIFO is half full, before any data is read. When the FIFO is half full, data are written in and read out. Phase jitter means that for a short period of time, the clock ratio will seem to increase, but this will be followed by a period where the ratio will seem slower. However, over a longer period of time, on average, the two clocks have a constant ratio. If the ratio is temporarily increased, more words are written into the FIFO than read from it, so the number of words within the FIFO will increase. However, this will be followed by a period where the ratio decreases, and the number of words within the FIFO also decreases. If the FIFO contains 64 entries, the number of samples in the FIFO, once the system is initialized, will be 32±1. If the jitter increases, this could be changed to 32±2 up to 32±n, where n depends on the severity of the jitter.
If the clocks are truly independent, the signal is resampled and filtered, which introduces loss in precision. Often the problem is avoided by reprogramming the PLL to the required sampling rate, thus avoiding the need to have two separate sampling rates. In summary, a FIFO of finite length can be used to compensate for a finite amount of jitter, but it cannot be used in the case where one clock drifts in respect to the second clock, because it would need to be of infinite length.
Systems, methods, products and techniques that permit ongoing compensation for clock drift and/or jitter in sample conversion would represent a significant advancement in the art. Moreover, providing such compensation with a design that is simple and can be easily implemented in existing Farrow combiner architectures likewise would constitute a significant advancement in the art.